The present invention relates to a method for planning a layout for an LSI pattern with optical proximity corrections ensured, a method for generating mask data and a method for forming an LSI pattern using these methods.
Recently, as a semiconductor large-scale integrated circuit (LSI) device has been downsized, a photolithographic step, which is one of the main process steps of an LSI fabrication process, has been affected by optical proximity effects more and more seriously. Specifically, a deviation of a feature size of a pattern actually transferred onto a resist from that of a mask pattern formed on a reticle has almost reached a non-negligible level. That is to say, if the feature size of an originally designed pattern is automatically applied to the mask pattern, then the size of the actually transferred pattern is likely to deviate from the originally designed one. This problem is particularly noticeable in a transistor, which plays a key role in determining the operability of an LSI. In this specification, a feature size of a pattern originally designed will be called a “designed size”, that of a pattern formed on a reticle or mask a “mask size” and that of a pattern actually transferred onto a resist an “actual size”, respectively.
Furthermore, every time an LSI of a new generation alternates with one of an older generation, the feature size of the LSI should be reduced discontinuously. For example, process technology of 0.18 μm generation has lately alternated with that of 0.25 μm generation. In this manner, a transistor feature size like the gate length thereof is usually reduced by about 70%. Whenever the gate length is reduced in this manner, one expects that the area of a cell implementing a circuit with the same function can also be reduced by about 50%, which is the square of 70%. This shrinkage rate is achievable by introducing a state-of-the-art exposure system using a radiation source with an even shorter wavelength or by improving the lithographic process itself.
These days, however, it has become more and more difficult to attain this shrinkage rate just by introducing a new system or improving the process. This is because the increase in deviation of an actual size from a mask size often prevents design rules, which are defined to ensure proper circuit operation, from achieving the 70% shrinkage rate. Examples of the design rules include the size of an extension of a gate and a contact margin.
FIG. 20(a) illustrates an originally designed pattern 100A and an actually transferred pattern 100B of an ordinary field effect transistor (FET). As shown in FIG. 20(a), the designed pattern 100A includes a gate pattern 101 to be shaped into a gate layer and an active layer pattern 102 to be shaped into an active layer. In the actually transferred pattern 100B, the width of the gate pattern 111 is smaller than its originally designed size, and both edge portions 111a of the gate pattern 111 no longer exist. If the portions of the gate pattern 111 overlapping with the active layer pattern 112 have been partially lost this way, then the transistor cannot operate normally.
To solve such a problem, extensions 101a are provided for both edges of the gate pattern 101 so as to extend from the active layer pattern 102 in the gate width direction as shown in FIG. 20(b). As the size of a line pattern, which is called a “gate length 101b” decreases, the areas of the edge portions of the gate pattern 101 to be lost increase. In other words, the size 101c of the extensions 101a does not decrease proportionally to the gate length 101b. Accordingly, when the gate length 101b is to be reduced, the size 101c of the extensions 101a of the gate pattern 101 should be increased to ensure proper operation for the transistor. Thus, it has become more and more difficult for the design rule concerning the extension size 101c to achieve the 70% shrinkage rate.
In spite of the circumstances such as these, the design rule is still defined based on the deviation of an actual size from a mask size. For example, the design rule is defined by the 70% shrinkage rate compared to the previous generation. Thus, to reduce the total area of the circuit patterns, the design rule defined based on the 70% shrinkage rate is prioritized and applied to even a pattern that cannot satisfy the design rule completely, e.g., the extension size 101c of the gate pattern 101.
Thereafter, a cell library is made up of a plurality of circuit patterns that have been designed in accordance with the design rule. LSI chip data is generated using the cell library to determine final conditions for the fabrication process. Based on these final process conditions, the deviation of an actual size from a mask size, which has been caused due to proximity effects, is estimated, thereby generating data for a mask layout that has been modified to eliminate the deviation of the actual size from the designed one. In this case, the actual sizes are estimated relative to the mask sizes using empirical models that reflect various conditions for estimating the actual sizes under predefined process conditions.
For example, in a portion of a circuit pattern where an actual size is thinner than its mask size, the mask size is thickened compared to the originally designed one. Conversely, in a portion of a circuit pattern where an actual size is thicker than its mask size, the mask size is thinned compared to the originally designed one. A mask pattern that is formed in view of optical proximity effects in this manner is called an “optical proximity corrected (OPC)” pattern.
According to the prior art method for generating LSI mask data, however, it is not until all the circuit patterns have been defined (i.e., while mask pattern data is being generated) that the OPC patterns are made. Thus, the OPC patterns could not be formed in some cases.
For example, consider a case shown in FIG. 20(a) where the edges of the gate pattern 101 disappear. In such a situation, even if the mask size for the extensions 101a of the gate pattern 101 should be corrected to match its actual size with the size originally designed for the circuit pattern, the size 101c of the extensions 101a could not be changed. For instance, this size change is impermissible if the space between the extensions 101a and surrounding patterns thereof is of the required minimum size defined by the resolution limit.
Furthermore, the prior art method for generating mask data has various drawbacks including the following:
(1) A design rule defined without taking proximity effect corrections into account would result in an excessively increased mask size.
The proximity effects on the gate pattern can be compensated for by various techniques other than the extension of the extensions. For example, where gates are laid out with relatively wide space interposed therebetween, a hammerhead pattern may be added to each extension of a gate pattern that is not located over the active layer of a transistor. This hammerhead pattern does hot extend the extension in the gate width direction, but expands only the edges of the extension in the gate longitudinal direction, thereby preventing the actual size of the gate pattern from shrinking too much at its edges in the gate width direction. In this manner, the proximity effect corrections can be made not only by compensating for the deviation of the actual size from the mask size but also by minimizing the deviation. Accordingly, if the size deviation was simply expected and a design rule was defined based on the result without estimating how much the deviation can be reduced by forming an OPC pattern, then the mask size determined would be unnecessarily large.
(2) In general, circuit patterns are made in accordance with a basic pattern placement rule and process conditions are defined to minimize a variation in sizes of patterns actually formed and a deviation of each actual size from its mask size. However, another pattern placement rule, which is different from that applied to the definition of the process conditions, is applied to OPC patterns. Thus, the process conditions defined are not always best suited to the placement rule for the OPC patterns.
Suppose circuit patterns have been defined with a pattern-to-pattern space minimized but the actual size of the space is larger than the originally designed one. In such a case, to make the size of the space between OPC patterns smaller than that once defined for the circuit patterns, the minimum space between the OPC patterns should be reduced from the minimum pattern-to-pattern space that was defined when the process conditions were determined. Accordingly, if the process conditions did not change at all, then the size of a pattern actually formed using the OPC pattern should almost match the size originally designed for the circuit pattern. Actually, though, the process conditions are variable during the fabrication process, thus making the actual size non-uniform due to the variation. This is because if an actual size is reduced, then optimum process conditions usually change to minimize the size non-uniformity due to the variation of process conditions. In an extreme case, even a basic exposure method such as super-resolution exposure or phase shift masking should be changed to suppress the size non-uniformity.
(3) Although final process conditions for an LSI are determined just before the actual fabrication thereof, details of OPC patterns cannot be defined until specific process conditions are determined.
In developing an LSI, design of circuit patterns to be registered at a cell library is started as early as more than 6 months before the fabrication of the LSI. However, since the process conditions are determined just before the fabrication, details of OPC patterns cannot be defined at an early stage. Accordingly, it is difficult to design circuit patterns for a cell library in view of final OPC patterns to solve the problem (1).
(4) An OPC pattern is made based on only a deviation of an actual size obtained under predetermined process conditions from a size originally designed for a circuit pattern. A design rule, which is ordinarily defined such that a feature size of the previous generation should be reduced by 70%, is applied to the circuit pattern. Although the 70% shrinkage may be effectively applicable to some LSI's, other LSI's may require a different shrinkage rate.
For example, in making an LSI with the same function and the same chip area based on a new design rule, that LSI might be obtained at a shrinkage rate of 50%. Furthermore, in an actual circuit pattern, the actual size does not have to exactly match the originally designed one in every part of the circuit. That is to say, some parts of a circuit may require an exact match between the actual and designed sizes to ensure proper operation for the circuit, but other parts thereof may allow some size deviation. Accordingly, if a circuit is designed such that all the actual sizes thereof are reduced by 70% compared to the older generation, then unnecessarily stringent conditions will be imposed on the LSI fabrication, thus making it much harder to obtain a desired LSI.